Final report

The report should provide:

 - description, schematics and layout of each PLL sub-sublock,

- the reasoning of sizing the transistors in the charge-pump and other modules,

- determination of the VCO frequency range and VCO constant of proportionality,

- the reasoning of sizing the loop filter components,

- schematic, layout view of the entire PLL,

- explain and justify layout techniques for reducing noise coupling and matching  (if used),

- post-layout simulations results. Comment and explain the results, and compare them with the schematics simulations.

 

The report must be considered as a stand-alone document. It should be well written so it gives the reader a complete view of what you have  done, what problems you encountered, how you approached them, and solved.

There is no page limitation of the report. Provide explanation to each figure you include in the report. 

 

The report should show that you understand how the PLL submodules work,  understand the principle of the operation of the PLL, and what are the limitations of your design. 

 

If the PLL does not operate properly, explain why.

 

In addition the location of all design files should be listed (library path).  You can find your libraries paths in the file cds.lib located in your Cadence folder. 

 

The organisation of the project and the distribution of responsibility within the group must also be included