Project outline can be downloaded here.
It maid take a while for us to answer your email, it is good to try to find the answers on the net or in the manuals while you are waiting for us.
Some useful manuals:
1) Virtuoso? Schematic Composer User Guide
2) Cadence? Analog Design Environment User Guide
3) Library Manager User Guide
It should not be difficult for you to find them online.
Some remarks on assignment 1:
- verilog-A is recommended because you can make ideal testbenches easily with it.
- You can some tutorial documents about verilog-A from Lund University here:
http://www.eit.lth.se/index.php?id=241&ciuid=369&coursepage=1799&L=1.
- You may need to map the library on Cadence before using it. Go to (Edit->Library Path),
Library name: “INF4420Project”
Library path: where your library is.
- Example verilog-A code of a 2-bit counter can be found here.
Some remarks on assignment 2:
- A guideline for extracting uCox can be found here.
- You are not restricted to use clocked (latched) comparator (i.e. you can use continuous-time comparator). But you have to make the additional module(s) required in verilog-A to make the whole system work, we need to reset the comparator after conversion.
- A guideline for Monte Carlo simulation can be found here.
- A tutorial of frequency response can be found here.
- You can find some information about how to test your comparator (not apply to the latched type) here.
Some remarks on assignment 3
- If you are using the resistor/capacitor models provided by TSMC in your schematic design you can't generate the complete netlist without adding an additional source file, see here.
- An example project report can be found here.
- Some remarks on PEX can be found here.
Some remarks on assignment 4
- Before you do the whole ADC simulation, you need to change the top level schematic a bit, see here.